United States Semiconductor Corporation (US-Semi) possesses a unique radiation hardening (rad hard) manufacturing process that can be applied to any conventional CMOS circuit to produce enhanced circuits for use in both military and civilian satellites and other wireless communication applications.
The satellite industry has been burdened with lack of access to the more advanced, faster, more powerful commercial integrated circuits because of unknown or poor radiation performance. Satellite and avionics designers have a need for a process that will allow them to use the commercial devices and systems currently available to terrestrial users but that will also guarantee radiation performance.
The process instills dramatic improvements in chip tolerance of radiation effects, independent of the fabrication process. It enables satellite and military system designers to use commercial parts that may not have been available in the past because of radiation performance problems. RHI-NO™ (Radiation Hardened Integrated circuit-NO redesign) will also be deployed in the development of proprietary families of chips and multi-chip modules, directed at high volume customer requirements.
THE RHINO PROCESS
With the US Semiconductor process, wafers are fabricated normally through the IC manufacturer’s standard process. After the wafer is manufactured, it is sent to US Semiconductor where it is cleaned, planarized and a glass wafer is attached to the top side, see Figure 1 below. The back side is then thinned by lapping and etching. The final illustration on Figure 1 shows the device after these steps by US Semiconductor. The proprietary process allows the electrochemical etch to be controlled into the active region of the chip. After passivation a mask is used to expose the bond pads. After pad etching, the wafer is sawed and packaged normally.
One additional concern from this process is its effect on the electrical characteristics of the wafer. Figure 2 below shows preliminary electrical data from a wafer that had been thinned using the described method. As is shown by the IDS (source to drain current) versus VGS (source to gate voltage) curve, analysis shows no negative impact to electrical performance due to the thinning process. Sub-threshold leakage is actually improved.
Figure 1 – Wafer Processing
Figure 2. Comparison of electrical characteristics of wafer before and after thinning
Strategically, an element of risk to this methodology is the provision of wafers from manufacturers. US Semiconductor has received consistently positive feedback from manufacturers, regarding supply of undiced finished wafers. Supply of completed, unpackaged wafers is not the normal distribution for most semiconductor manufactures, but appears to be a manageable issue to US-semi because the process opens up new market applications to the chip manufacturers.
One of the principal limitations to the advancement of information technology solutions by satellite has been the narrow range of rad hard circuits available. Of the millions of standard and semi-custom products, not including application specific integrated circuits (ASIC), that a product designer normally can resource, only a fraction of these have been duplicated by the current rad hard device suppliers. This forces the designer to limit functionality of the design, to select expensive and heavy shielding options, or to use elaborate, heavy, and expensive circuit redundancy schemes.
The bulk CMOS process produces a circuit on a 500 micron thick silicon wafer, implanting the circuit in a thin surface layer of the silicon substrate. The conductive silicon substrate creates problems of its own. Parasitic effects ensue, including high power consumption with needed increases in switching speed, high frequency signal handling problems, and circuit coupling. The drive toward rad hard systems on a chip, utilizing ever-smaller geometries, will clearly require different substrate solutions.
One direction has been in the use of Gallium Arsenide (GaAs). In its long history, however, its developers have not been able to overcome persistent manufacturing obstacles. Other, newer materials, such as silicon carbide and silicon germanium, suffer the same manufacturing obstacles along with the added burden of being many years away from being commercially useful. Silicon is still the substrate of choice. The question remains how to eliminate or minimize the undesirable effects.
Clearly, if transistors could be fabricated in thin air, as it were, ideal devices would result. In the case of radiation tolerance, the circuit would not be vulnerable to deterioration from exposure to ion bombardment, as this is a parasitic effect that is not shared by the circuit itself. Developers of Silicon On Sapphire (SOS), a silicon on insulator technology, have had some success in military and space applications They are limited by the demands of state-of-the-art circuits. The sapphire wafer has proven to be inhospitable to modern high density requirements and high manufacturing yield requirements.
Other approaches to SOI that have been examined are techniques known as wafer bonding and SIMOX (Separation by Implanted OXygen). These processes are complicated, time-consuming, and costly. These approaches require the insertion of an insulating oxide layer between existing layers of silicon. Wafer bonding sandwiches two oxidized bulk wafers together.
Developers stick with SIMOX and similar SOI technologies because they solve the problem of supporting smaller transistor needs. However, silicon dioxide is a poor thermal conductor. Even if the layer is kept very thin, heat degradation persists, as well as many other parasitic effects associated with silicon layer deployment. Moreover, SIMOX and the others are unable to use a standard semiconductor process. Therefore, both the process as well as the circuit requires redesign. The ideal solution would be a very thin silicon film, mounted on a mechanically stable and inert substrate that is thermal resistant, and uses standard, off the shelf parts. This, then, is the US-Semi solution.